In digital and video cameras, CMOS APSs are used to acquire images. An APS is defined as a solid state image sensor that has one or more active transistors within a pixel unit cell. This is in contrast to a passive pixel sensor that uses a simple switch to connect a pixel signal to a column. An APS provides lower noise, improved scalability and higher speed compared to passive pixel sensors.
In an APS, each pixel contains a photosensing means and at least one other active component. When light is incident on a pixel, a charge is created that is converted to a signal, either a voltage or current signal. The signal represents the amount of light incident upon a pixel.
FIG. 1 is a schematic of a portion of a conventional CMOS APS comprising transistors 104, 108, 112 and a photodiode 116. Although circuitry for only a single pixel is shown in FIG. 1, it will be understood that circuitry for a large number of pixels are normally included in an APS array. Light is coupled through a color filter (not shown) to the photodiode 116. Different colored filters are used in an APS array so that signals from different sets of pixels allow a color image to be created. The photodiode 116 changes the light to a charge having a magnitude that is proportional to the intensity of the light. The charge is converted into a voltage and passed to a column line.
Prior to acquiring an image, each pixel in the APS is reset. This is accomplished by driving a reset row line (Reset N) to a voltage, VDDP, where VDDP>VDD+VTHN, and VTHN is the threshold voltage of the transistor 104. This causes the transistor 104 to turn on and sets the voltage across the photodiode 116 to VDD. The voltage on the column line is called the dark or reference voltage level, VR, of the pixel. Next, the transistor 112 is turned on by driving Row N to VDDP and, with transistor 108 behaving as a source follower, the column line is set to the reference voltage level, VR. The reference voltage VR is stored at the beginning of a sense.
After the reference voltage VR is stored, the Reset N line is driven low, thus turning off the transistor 104 to isolate the photodiode 116 from VDD. The light striking the reverse biased photodiode 116 then generates electron-hole pairs that cause the voltage across the photodiode 116 to decrease. The voltage from the photodiode 116 is applied to the gate of the transistor 108, which couples the voltage to column line through the transistor 112, which is turned on by the high RowN signal. As a result, the decrease in the voltage across the photodiode 116 is sampled on the column line and this voltage is called an intensity voltage VI.
The time between the Reset N line being driven low and the intensity voltage, VI, corresponding to the intensity of the light striking the photodiode 116 being sampled on the column line is called the aperture time. Note that the dark signal corresponds to a large voltage (VDD−VTHN) on the column line while a bright signal corresponds to a lower voltage, less than (VDD−VTHN) on the column line.
FIG. 2 illustrates a conventional sample and hold circuit that can be used to sample and hold a reference voltage VR and an intensity voltage VI from an APS. The sample and hold circuit comprises transistors 204, 208 and hold capacitors 212, 216. The transistor 204 and the hold capacitor 212 are connected in series between a column line 220 and ground. Similarly, the transistor 208 and the hold capacitor 216 are connected in series between the column line 220 and ground.
When ResetN and RowN are high, the pixel's reference or dark voltage, VR, is placed on the column line 220. At this time, a sample and hold reference signal, SHR, is driven high, which turns on the transistor 204, thereby placing a sample of VR on the hold capacitor 212.
Next, ResetN transitions low to allow the photodiode 116 to change light into a corresponding charge. After the aperture time, a sample of the intensity voltage VI is placed on the column line 220. At this time, the sample and hold intensity signal SHI is driven high, which turns on the transistor 208, thereby placing a sample of VI on the hold capacitor 216.
Because each pixel in an imaging array will have slightly different characteristics, the differences in the intensity voltage VI for light having the same intensity can result in speckles in a resulting image. To eliminate this mismatch problem, images are created based on the intensity of the change of light during an aperture time. This is accomplished by subtracting the reference voltage VR from the actual measured signal or intensity voltage VI to accurately determine the light intensity applied to the pixel.
FIG. 3 is a schematic of a conventional circuit that uses the differences in VR and VI to accurately determine the light intensity applied to the pixel, and to generate a digital output Q by an A/D. As mentioned earlier, VR and VI are sampled and held on to capacitors 212 and 216, respectively. VR is then converted to a current IR by a voltage to current converter 308. Similarly, VI is converted to a current II by a voltage to current converter 312. The implementation of a voltage to current converter is well understood by those skilled in the art and thus will not be discussed in detail.
The currents IR and II flow through path R and path I, respectively, to a differential circuit 316. The differential circuit generates an output current IOUT, where IOUT=IR−II. IOUT is representative of the difference between VR and VI. The differential circuit 316 can be implemented using a current mirror circuit or other circuits well known to those skilled in the art. An A/D converter 320 receives IOUT and generates a digital output Q. Thus, the digital output Q is representative of the difference between VR and VI.
While the schematic of FIG. 3 eliminates the problem caused by the mismatches in pixel characteristics, the sampling circuit, having two separate paths, i.e., reference path and intensity signal path, is also subject to a mismatch. Each voltage to current converter has a different random offset that creates a mismatch between the two paths, thereby degrading the resulting the image. Also voltage to current converter has a varying transconductance (gm=IR/VR or IS/VS) that degrades the image. The schematic of FIG. 3 does not eliminate the mismatches in the paths.
FIG. 4 illustrates the mismatch between the reference path and the intensity path. In FIG. 4, a 20 mV offset is in series with the intensity path. The offset voltage, that may be positive or negative, simply represents the mismatch in the paths.
Accordingly, there is a need for a system and a method that reduce the mismatch between the reference path and signal path in an APS.